ANANANT SYSTEMS  /  DETERMINISTIC · RISC-V · DSP · 5G · 6G · SMALL CELL · EDGE-AI

Deterministic compute
and connectivity for
machines, networks, floors.

Silicon for applications where power, latency and cost are the limiting constraints. Connectivity products are in production; perception products follow on the same architecture.

01The problem

Four constraints that apply at the same time.

Industrial edge systems — a machine on a factory floor, a small cell on a pole, a camera on a mobile robot — operate under all four of the following simultaneously. Most processors are designed to satisfy three.

P1Performance

Real-time signal processing and AI inference on live sensor streams, concurrently rather than in sequence.

P2Power

Milliwatts at the sensor, single-digit watts at the node. No active cooling and often no mains supply.

P3Programmability

Standards and models change during a deployment’s service life. Fixed-function silicon cannot follow them.

P4Determinism

A bounded, repeatable response time. Control loops and safety functions cannot tolerate variable latency.

General-purpose processors trade these against each other. Fixed-function accelerators introduce timing variance at the hand-off. Multi-chip platforms carry the cost of each boundary in power, latency and bill of materials.

02Our approach

Why we work on this.

01

Connectivity and perception share the same mathematics

MIMO demodulation and vision pipelines are both dense linear algebra on streaming data under a deadline. Transforms, matrix multiplies and nonlinear activations are common to both, so one datapath can serve both without compromise.

02

Existing roadmaps target other sockets

The largest processor roadmaps are optimised for data centre and handset workloads, where the constraints and volumes differ. Industrial edge designs are typically served by parts adapted from those markets.

03

The team has built this class of silicon

Our founding team spent two decades architecting modem platforms shipped in over four billion devices, with no re-spin in any generation the CTO architected.

03What we build

One architecture, two products.

We design our own DSP. Connectivity, perception, the systems and the software platform are all composed from that one compute unit, so software written for the first generation runs on the third.

computeOur DSP and edge-AI inference on one datapath and one toolchain.
connectDeterministic 5G connectivity from the same silicon architecture.
cognizePerception with a bounded response time, at camera-class cost and power.
>2×THROUGHPUT VS INCUMBENT DSP
⅓ · ⅓POWER · COST
>50%LOWER SYSTEM POWER VS MULTI-CHIP PLATFORMS

04Roadmap

Product journey.

Completed milestones, work in progress, and committed dates.

Gen 1 · FPGA validation, integrated with commercial L2/L3 stacks2023–25
Gen 1 · v1 silicon in production2026
Gen 1 · v2 — power-optimised revisionIn progress
Gen 2 · Architecture committed — connectivity and perception on one dieJUL 2026
Gen 2 · Evaluation kits and silicon sampling in OEM labsH2 2027
Gen 3 · Radio integrated on-die2028 →

complete    in progress    committed